1. Field of the Invention
This invention realates to computer bus interface systems and, more particularly, to apparatus and methods for minimizing the time necessary when controlling devices across a bus interface in a computer system.
2. History of the Prior Art
U.S. Pat. application Ser. No. 07/599,265, entitled APPARATUS AND METHOD FOR LOADING COORDINATE REGISTERS FOR USE WITH A GRAPHICS SUBSYSTEM UTILIZING AN INDEX REGISTER, Priem and Malachowsky, filed Oct. 16, 1990, describes a graphics accelerator adapted to process data as rapidly as information is capable of being accepted by a video frame buffer for a computer output display. Each stage of the graphics accelerator described therein must be capable of operating at as high a speed as possible in order to maintain the overall speed of the graphics accelerator. Consequently, the interface stage between the central processing unit and the graphics accelerator must be capable of operating at a speed which processes data at the aforementioned rate.
The steps that the central processing unit associated with the typical graphics accelerator of the prior art must accomplish to initiate any particular operation by which information is written to the computer output display are many. It must at least 1) check the status of the graphics accelerator to determine whether the data registers are ready to receive data, 2) write all of the data necessary to the registers of the graphics accelerator, 3) read the status register of the graphics accelerator to find out whether any exceptions exist which would make the operation impossible to accomplish, and 4) write the command to the graphics accelerator to initiate its operation. A typical wire operation for tow pieces of data, such as and X and a Y value of a point to be displayed, requires at least five individual accesses by the central processing unit of the graphics accelerator. It will be appreciated that such an operation will require a substantial amount of time, particularly because read accesses require a great deal of time.
If the interface between the central processing unit and the graphic accelerator requires such a period of time in order to accomplish the initiation of each operation, then the interface cannot possibly transfer data at a rate sufficient to match the bandwidth of the video frame buffer. Moreover, with so many individual accesses involved, if the interface time to initiate any particular operation is long there are a great number of instances in which another task might run in a multi-tasking system before the current task can finish. This can lead to problems of stale data and excessive context save/restore overhead.